This invention relates to an address control device for use between an execution processing unit and a memory section in an information processing system.
An information processing system of the type described often adopts pipeline control in order to process a succession of instructions at a high speed. To this end, an execution processing unit carries out prefetch or lookahead of instructions from a main memory prior to execution of the prefetched instructions. This shows that the main memory is inevitably accessed by the execution processing unit.
A virtual address is produced from the execution processing unit on accessing the main memory and must therefore be converted or translated into a corresponding real address of the main memory. In other words, address conversion or translation of a virtual address into a real address is indispensable for such an information processing system and may be made by looking up an address conversion or translation table stored in the main memory. However, such a table look-up makes the pipeline control difficult because the main memory must be accessed each time when the address conversion is carried out.
In order to make the pipeline control possible, an address control device is used to carry out address conversion of a virtual address into a real address at a high speed and is operative in cooperation with a cache memory. A combination of the main memory and the cache memory will be collectively called a memory section.
A conventional address control device comprises a translation-lookaside buffer (TLB) which keeps or stores a predetermined number of entries in relation to virtual addresses already issued from the execution processing unit. With this structure, the translation lookaside buffer is at first looked up by a virtual address and quickly carries out address conversion of the virtual address into a real address as long as an entry is stored in correspondence to the virtual address in question.
Stated otherwise, the address conversion table of the main memory is accessed only in the absence of any entry corresponding to the virtual address in question. This serves to minimize a waste of time which might occur due to an access operation of the main memory.
Herein, let a conditional branch (a branch-on-condition) instruction be prefetched as a prefetched instruction in the execution processing unit. Such a prefetch operation might be carried out about the conditional branch instruction on the assumption that prediction is made about either success, namely, satisfaction of a branch condition or unsuccess, namely, failure of the branch condition. In addition, instructions and operands for the instructions might also be prefetched in the cache memory in accordance with the prediction carried out for the conditional branch instruction. Under the circumstances, such prediction of a branch condition might often be wrong or end in failure.
In a conventional information processing system, the prefetched operands might be cancelled on occurrence of the wrong prediction by sending a cancellation indication from the execution processing unit to the address control device. This serves to avoid supply of the prefetched operands to the execution processing unit in connection with the wrong prediction.
Herein, the address control device carries out an address storing operation for a predetermined duration when the translation lookaside buffer does not store an entry in relation to an input virtual address. When the above-mentioned cancellation indication is supplied from the execution processing unit to the address control device during the address storing operation, the address storing operation might be interrupted in the address control device under way to be cancelled. Such interruption of an address storing operation requires complex control in the address control device.
Moreover, even when prediction is wrong once about a branch condition of a conditional branch instruction, it often happens that similar prediction is judged to be correct when the conditional branch instruction in question is carried out either again or a certain number of times. In this event, a branch operation must be directed towards the previously prefetched operands which have already been cancelled in the translation lookaside buffer. Accordingly, the address storing operation interrupted under way should be redone from a beginning of the address storing operation. This shows that the address storing operation undesirably wastes a time in the address control device, which results in degradation of performance in the information processing system.